Primary Processor

Spec hygiene (CLAUDE.md rule 1). This document does not restate concrete hardware values (clock speed, RAM, runtime envelope, etc.). Those live in CLAUDE.md’s Canonical Hardware Specification. Any value that appears inline is a bug — file an issue and fix it.

Role

The Raspberry Pi Zero 2 W is the sole primary processor for the KN-86 Deckline. It runs Linux userspace, owns the nOSh runtime (mission board, phase chain, deck state, Fe VM execution), drives the primary display over HDMI, hosts the internal USB hub for keyboard + cartridge bridge, and commands the Pi Pico 2 coprocessor for realtime I/O.

Architecture summary: Pi = compute brain. Pico = realtime I/O front-end (see coprocessor.md).

For the canonical processor specification (model, cores, clock, RAM, connectivity), see CLAUDE.md Canonical Hardware Specification — Processor row.

Why Zero 2 W

Zero W (original): Insufficient compute for the desktop emulator path; nOSh’s UI animations and PSG synthesis benefit meaningfully from the Cortex-A53 quad core.
Pi 4: Overpowered and too physically large to fit the Pelican 1170’s interior envelope (see enclosure.md). Power draw would also compromise the battery runtime target.
Zero 2 WH (pre-soldered header variant): Functionally identical to Zero 2 W for our purposes; either is acceptable at bench-rig scale. The build uses whichever is available.

Interfaces

Interface	Connects to	Notes
mini-HDMI	Elecrow 7” primary display	See `primary-display.md`.
USB OTG	Internal USB 2.0 hub IC (TUSB2036 / FE1.1s)	Hub fans out to keyboard controller (see `keyboard.md`) + USB-to-SD bridge IC (see `cartridge-interface.md`).
UART0 (GPIO14 TX, GPIO15 RX)	Pi Pico 2 coprocessor at 1 Mbps	Command link per ADR-0017. See `coprocessor.md` and `software/api-reference/grammars/coprocessor-protocol.md`.
GPIO22, GPIO23	Pico 2 BOOTSEL + RESET control lines	Drives the Pi-mediated Pico flash flow. Pin assignment is TBD during prototype bring-up if a conflict surfaces (ADR-0017 §6 + Known Unknowns #2).
microSD	A/B partitioned system image + `/home/shared`	See ADR-0011 for partition layout and `device/os/` for the OS image build.
Wi-Fi (onboard)	Time sync, OTA updates, dev-mode SSH	Production mode masks SSH; see `build-specification.md` §5.
5V VIN	Main 5 V rail from the Waveshare UPS Module 3S (ADR-0038)	See `power.md`.
I²C (battery monitor)	UPS module INA219	nOSh reads pack voltage/current/power for the Row-0 battery glyph (ADR-0038). See `power.md`.

GPIO budget (post-coprocessor)

The Pi gives up SPI0 (was driving the SSD1322 per pre-ADR-0017 ADR-0015 §1) and the I2S pins (BCLK / LRCLK / DOUT — was driving the MAX98357A directly). It gains the four UART0 + control pins for the Pico link. Net: −5 freed, +4 claimed — slight net reduction in claimed Pi GPIOs (ADR-0017 §7).

Free Pi SPI0 / SPI1 / I2S pins remain available for a future peripheral (no current claim).

Power

The Pi draws from the main 5V rail at its VIN pin. Typical draw and runtime envelope are canonical values — see CLAUDE.md Battery row. The post-coprocessor envelope is the load-bearing one (the pre-coprocessor figures are pre-2026-04-24 history; see coprocessor.md for the runtime-band shift). Power topology and idle behavior live in power.md.

The Zero 2 W has no built-in fuel gauge, but battery state is read from the Waveshare UPS Module 3S’s onboard INA219 over I²C (voltage/current/power) per ADR-0038 — this replaces the prior resistor-divider + MCP3008 ADC plan. nOSh polls at ~1 Hz. Below threshold: low-battery glyph on Row 0, best-effort deckstate checkpoint, clean shutdown before protection cuts power.

Compute model

The Pi runs:

Linux userspace (Raspberry Pi OS or pi-gen-built variant — see device/os/).
nOSh runtime (single C/SDL3 process; see software/runtime/).
Fe VM for cartridge Lisp execution (ADR-0001, ADR-0004).
Coprocessor daemon owning /dev/serial0, exposing the Pico command surface to nOSh (ADR-0017 §F3).
udev subscriber for cartridge insertion / removal events (see cartridge-interface.md).

Cartridge code does not observe the Pi/Pico boundary — the NoshAPI FFI surface (ADR-0005) is identical regardless of which side fulfills the call.

Bring-up

Stage 0 in build-specification.md §4. Headless Wi-Fi + SSH from dev box, microSD provisioning, kn86 userspace install. The Pi-side bring-up completes before the coprocessor (Stage 1c — see coprocessor.md) and the auxiliary display (auxiliary-display.md).

Sourcing

BOM line 1 in sourcing-guide.md. Suppliers: Adafruit, Pimoroni, Raspberry Pi direct. Order 2 units up front (one for the rig, one as spare) — Pi global supply spikes into shortage during chip crunches.